In a typical active matrix display, each pixel has a thin film transistor (TFT) with a gate electrode thereof being connected to a gate line in a horizontal direction and a source electrode thereof being connected to a data line in a vertical direction. When a gate scan pulse is applied to a gate line, a row of TFTs connected to this gate line is turned on, such that grayscale voltages on respective data lines are written to the row of pixels.
Due to manufacturing process, defect areas (or “mura”) where luminance is significantly different than other areas at the same grayscale voltage tend to be formed on the display panel. FIG. 1 is a schematic view showing a display panel 100 on which several defect areas are present. With the same grayscale voltage being applied to respective pixels of the display panel, there are still some positions where the luminance is darker. As shown in FIG. 1, the luminance of a central area 110 is significantly lower than the remaining areas. Such a display defect is undesirable.